The invention relates to a method of manufacturing a semiconductor device comprising a semiconductor body including a bipolar transistor having a base region, a collector region and an emitter region, a monocrystalline silicon substrate being provided with a first insulating layer, a polycrystalline layer of silicon and a second electrically insulating layer, an opening being formed in this layer structure, which opening extends to a monocrystalline part of the semiconductor body, the bottom of the opening being provided with a third insulating layer, at least a part of the base region being formed via said opening by providing doping atoms in the monocrystalline part of the semiconductor body, and the emitter region being formed by means of a further opening in the third electrically insulating layer, which opening is smaller than the first opening in the monocrystalline part of the semiconductor body. It is noted that, in this application, the term "insulating" is to be taken to mean "electrically insulating".
Such a method is known from United States patent specification U.S. Pat. No. 5,512,785, published on Apr. 30, 1996. In said document, a description is given of a method of manufacturing a so-called double poly bipolar transistor: reference is made, in particular, to the description of FIG. 6 and FIG. 7. Such a transistor is obtained by making an opening in a stack of layers comprising a first insulating layer, a polycrystalline layer of silicon and a second insulating layer, which opening extends to a monocrystalline part of the semiconductor body. A third insulating layer (see FIG. 7) is subsequently provided on the bottom of this opening by means of thermal oxidation of the semiconductor body. A part of the base region of the transistor is formed by subsequently launching doping atoms, through the third insulating layer, into the monocrystalline part of the semiconductor body. The polycrystalline layer is provided, in the above-mentioned opening, with so-called spacers of (doped) polycrystalline silicon by means of which the polycrystalline layer is connected to the monocrystalline part of the semiconductor body, said spacers forming, in the above-mentioned opening, another part of the base region as a result of out-diffusion. After providing further spacers in the opening, and after forming a window in the third insulating layer, a further polycrystalline layer of silicon is provided in the opening, thereby forming the emitter region in the monocrystalline part of the semiconductor body, which further polycrystalline layer of silicon serves as the connection region of said emitter region.
A drawback of the known method resides in that the transistors manufactured in accordance with said method have electrical characteristics, such as a base current which is (too) high, which exhibit a relatively great spread. In view of the yield, this is undesirable, so that the transistors manufactured by means of the known method are relatively expensive.